Quantum-well-based semiconductor devices

ABSTRACT

Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/571,121, filed Aug. 9, 2012, which is a divisional of U.S. patentapplication Ser. No. 12/632,498, filed Dec. 7, 2009, now U.S. Pat. No.8,258,543, issued on Sep. 4, 2012, the entire contents of which arehereby incorporated by reference herein.

TECHNICAL FIELD

Embodiments of the invention are in the field of Semiconductor Devicesand, in particular, quantum-well-based semiconductor devices and methodsof forming quantum-well-based semiconductor devices.

BACKGROUND

For the past several decades, the scaling of features in integratedcircuits has been a driving force behind an ever-growing semiconductorindustry. Scaling to smaller and smaller features enables increaseddensities of functional units on the limited real estate ofsemiconductor chips. For example, shrinking transistor size allows forthe incorporation of an increased number of memory devices on a chip,lending to the fabrication of products with increased capacity. Thedrive for ever-more capacity, however, is not without issue. Thenecessity to optimize the performance of each device becomesincreasingly significant.

Quantum-well devices formed in epitaxially grown semiconductorhetero-structures, such as in III-V material systems, offerexceptionally high carrier mobility in the transistor channels due tolow effective mass along with reduced impurity scattering by deltadoping. These devices provide high drive current performance and appearpromising for future low power, high speed logic applications.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross-sectional view of a quantum-well-basedsemiconductor device, in accordance with an embodiment of the presentinvention.

FIG. 2 illustrates a cross-sectional view of a quantum-well-basedsemiconductor device, in accordance with an embodiment of the presentinvention.

FIG. 3 is a Flowchart representing operations in the fabrication of aquantum-well-based semiconductor device, in accordance with anembodiment of the present invention.

FIG. 4A illustrates a cross-sectional view representing an operation inthe fabrication of a quantum-well-based semiconductor device, inaccordance with an embodiment of the present invention.

FIG. 4B illustrates a cross-sectional view representing an operation inthe fabrication of a quantum-well-based semiconductor device, inaccordance with an embodiment of the present invention.

FIG. 4C illustrates a cross-sectional view representing an operation inthe fabrication of a quantum-well-based semiconductor device, inaccordance with an embodiment of the present invention.

FIG. 4D illustrates a cross-sectional view representing an operation inthe fabrication of a quantum-well-based semiconductor device, inaccordance with an embodiment of the present invention.

FIG. 4E illustrates a cross-sectional view representing an operation inthe fabrication of a quantum-well-based semiconductor device, inaccordance with an embodiment of the present invention.

FIG. 4F illustrates a cross-sectional view representing an operation inthe fabrication of a quantum-well-based semiconductor device, inaccordance with an embodiment of the present invention.

DETAILED DESCRIPTION

Quantum-well-based semiconductor devices and methods of formingquantum-well-based semiconductor devices are described. In the followingdescription, numerous specific details are set forth, such as materialregimes and device characteristics, in order to provide a thoroughunderstanding of embodiments of the present invention. It will beapparent to one skilled in the art that embodiments of the presentinvention may be practiced without these specific details. In otherinstances, well-known features, such as patterning processes, are notdescribed in detail in order to not unnecessarily obscure embodiments ofthe present invention. Furthermore, it is to be understood that thevarious embodiments shown in the Figures are illustrativerepresentations and are not necessarily drawn to scale.

Disclosed herein are quantum-well-based semiconductor devices. In oneembodiment, a quantum-well-based semiconductor device includes ahetero-structure disposed above a substrate and having a quantum-wellchannel region. A source and drain material region is disposed above thequantum-well channel region. A trench is disposed in the source anddrain material region separating a source region from a drain region. Abarrier layer is disposed in the trench, between the source and drainregions. A gate dielectric layer is disposed in the trench, above thebarrier layer. A gate electrode is disposed in the trench, above thegate dielectric layer. In one embodiment, a quantum-well-basedsemiconductor device includes a hetero-structure disposed above asubstrate and having a quantum-well channel region. A barrier layer isdisposed directly on the quantum-well channel region. A source and drainmaterial region is disposed above the barrier layer. A trench isdisposed in the source and drain material region separating a sourceregion from a drain region. A gate dielectric layer is disposed in thetrench, between the source and drain regions. A gate electrode isdisposed in the trench, above the gate dielectric layer.

Also disclosed herein are methods of forming quantum-well-basedsemiconductor devices. In one embodiment, a method includes providing ahetero-structure disposed above a substrate and including a quantum-wellchannel region. A source and drain material region is formed above thequantum-well channel region. A trench is formed in the source and drainmaterial region to provide a source region separated from a drainregion. A gate dielectric layer is formed in the trench, between thesource and drain regions. A gate electrode is formed in the trench,above the gate dielectric layer.

In accordance with an embodiment of the present invention, a gate-lastflow is used to fabricate group III-V or germanium quantum-well fieldeffect transistor (QWFET) devices. This approach may enable one or moreof the following features: (1) all materials including source and drainmaterial are grown first and then a trench is etched in the source anddrain material to accommodate a gate electrode, (2) source and draingrowth is simplified because regrowth is no longer required and thepossible elimination of a barrier between a quantum well and a dopedsource and drain may be realized, (3) a high band gap barrier materialand a high K gate dielectric may be deposited later in the process flowand may be deposited by atomic layer deposition (ALD) or metal-organicchemical vapor deposition (MO-CVD), and (4) a gate-last flow may enablethe lowest thermal budget to be applied to the gate material or enable amore precise control on that operation since the operation is last inthat portion of the processing scheme.

In various embodiments presented herein, key features may include anetch of a gate trench, deposition of gate material by ALD or MOCVD, andan overall reduction in external resistance (Rext) since, in someembodiments, there is no barrier in the source and drain region and thesource and drain region is a highly doped group III-V or germaniummaterial. In an embodiment, approaches described herein enable avoidanceof the formation of dislocations and impurities in the source and drainregions that might otherwise occur if the source and drain regions wereregrown after an etch process. In one embodiment, some of the approachesdescribed herein enable deposition of a barrier material at the end-ofline processing in the process flow, reducing detrimental thermal impactof a gate electrode material. In one embodiment, some of the approachesdescribed herein enable the formation of a barrier layer only under agate stack region, between the gate stack and a quantum well, and notbetween source/drain regions and the quantum well. In accordance with anembodiment of the present invention, one or more of the gate-lastapproaches described herein enables the use of a barrier material thatwould otherwise deteriorate above approximately 500 degrees Celsius,e.g., would otherwise deteriorate at a temperature required for a sourceand drain anneal process.

In an aspect of the present invention, a semiconductor device includes aquantum-well channel region with a barrier layer covering only a portionof the quantum-well channel region. FIG. 1 illustrates a cross-sectionalview of a quantum-well-based semiconductor device, in accordance with anembodiment of the present invention.

Referring to FIG. 1, a quantum-well-based semiconductor device 100includes a hetero-structure 104 disposed above a substrate 102 andincluding a quantum-well channel region 106. A source and drain materialregion 108 is disposed above quantum-well channel region 106. A trench110 is disposed in source and drain material region 108 separating asource region 108A from a drain region 108B. A barrier layer 112 isdisposed in trench 110, between source and drain regions 108A and 108B.A gate dielectric layer 114 is disposed in trench 110, above barrierlayer 112. A gate electrode 116 is disposed in trench 110, above gatedielectric layer 114. In accordance with an embodiment of the presentinvention, hetero-structure 104 may be defined as a stack of one or morecrystalline semiconductor layers, such as the stack depicted in FIG. 1.

In an embodiment, trench 110 exposes the top surface of the quantum-wellchannel region 106, and barrier layer 112 is disposed directly on theexposed surface of quantum-well channel region 106, as depicted inFIG. 1. In another embodiment, however, source and drain material region108 is disposed directly on quantum-well channel region 106 (asdepicted), trench 110 is disposed only partially into source and drainmaterial region 108 leaving a portion of source and drain materialregion 108 at the bottom of trench 110 (not depicted), and barrier layer112 is disposed directly on the portion of source and drain materialregion 108 at the bottom of trench 110 (not depicted). In an embodiment,quantum-well channel region 106 includes a group III-V material, andsource and drain material region 108 includes a doped group III-Vmaterial region. In an embodiment, gate dielectric layer 114 is composedof a high-K material such as, but not limited to, aluminum oxide (Al₂O₃)or hafnium oxide (HfO₂). In an embodiment, gate electrode 116 is a metalgate electrode. In one embodiment, quantum-well channel region 106includes a group III-V material, and source and drain material region108 includes a doped group III-V material region, gate dielectric layer114 is composed of a high-K material such as, but not limited to,aluminum oxide (Al₂O₃) or hafnium oxide (HfO₂), and gate electrode 116is a metal gate electrode.

Substrate 102 may be composed of a material suitable for semiconductordevice fabrication. In one embodiment, substrate 102 is a bulk substratecomposed of a single crystal of a material which may include, but is notlimited to, silicon, germanium, silicon-germanium or a III-V compoundsemiconductor material. In another embodiment, substrate 102 includes abulk layer with a top epitaxial layer. In a specific embodiment, thebulk layer is composed of a single crystal of a material which mayinclude, but is not limited to, silicon, germanium, silicon-germanium, aIII-V compound semiconductor material or quartz, while the top epitaxiallayer is composed of a single crystal layer which may include, but isnot limited to, silicon, germanium, silicon-germanium or a III-Vcompound semiconductor material. In another embodiment, substrate 102includes a top epitaxial layer on a middle insulator layer which isabove a lower bulk layer. The top epitaxial layer is composed of asingle crystal layer which may include, but is not limited to, silicon(e.g., to form a silicon-on-insulator (SOI) semiconductor substrate),germanium, silicon-germanium or a III-V compound semiconductor material.The insulator layer is composed of a material which may include, but isnot limited to, silicon dioxide, silicon nitride or silicon oxy-nitride.The lower bulk layer is composed of a single crystal which may include,but is not limited to, silicon, germanium, silicon-germanium, a III-Vcompound semiconductor material or quartz. Substrate 102 may furtherinclude dopant impurity atoms.

Hetero-structure 104 may be defined as a stack of one or morecrystalline semiconductor layers, such as a compositional buffer layerwith a bottom barrier layer disposed thereon. The compositional bufferlayer may be composed of a crystalline material suitable to provide aspecific lattice structure onto which a bottom barrier layer may beformed with negligible dislocations. For example, in accordance with anembodiment of the present invention, the compositional buffer layer isused to change, by a gradient of lattice constants, the exposed growthsurface of semiconductor hetero-structure 104 from the lattice structureof substrate 102 to one that is more compatible for epitaxial growth ofhigh quality, low defect layers thereon. In one embodiment, thecompositional buffer layer acts to provide a more suitable latticeconstant for epitaxial growth instead of an incompatible latticeconstant of substrate 102. In an embodiment, substrate 102 is composedof single-crystal silicon and the compositional buffer layer 104 iscomposed of a layer of InAlAs having a thickness of approximately 1micron. In an alternative embodiment, the compositional buffer layer isomitted because the lattice constant of substrate 102 is suitable forthe growth of a bottom barrier layer for a quantum-well semiconductordevice.

The bottom barrier layer may be composed of a material suitable toconfine a wave-function in a quantum-well formed thereon. In accordancewith an embodiment of the present invention, the bottom barrier layerhas a lattice constant suitably matched to the top lattice constant ofthe compositional buffer layer, e.g., the lattice constants are similarenough that dislocation formation in the bottom barrier layer isnegligible. In one embodiment, the bottom barrier layer is composed of alayer of approximately In_(0.65)Al_(0.35)As having a thickness ofapproximately 10 nanometers. In a specific embodiment, the bottombarrier layer composed of the layer of approximatelyIn_(0.65)Al_(0.35)As is used for quantum confinement in an N-typesemiconductor device. In another embodiment, the bottom barrier layer iscomposed of a layer of approximately In_(0.65)Al_(0.35)Sb having athickness of approximately 10 nanometers. In a specific embodiment, thebottom barrier layer composed of the layer of approximatelyIn_(0.65)Al_(0.35)Sb is used for quantum confinement in a P-typesemiconductor device.

Quantum-well channel region 106 may be composed of a material suitableto propagate a wave-function with low resistance. In accordance with anembodiment of the present invention, quantum-well channel region 106 hasa lattice constant suitably matched to the lattice constant of thebottom barrier layer of hetero-structure 104, e.g., the latticeconstants are similar enough that dislocation formation in quantum-wellchannel region 106 is negligible. In an embodiment, quantum-well channelregion 106 is composed of groups III (e.g. boron, aluminum, gallium orindium) and V (e.g. nitrogen, phosphorous, arsenic or antimony)elements. In one embodiment, quantum-well channel region 106 is composedof InAs or InSb. Quantum-well channel region 106 may have a thicknesssuitable to propagate a substantial portion of a wave-function, e.g.suitable to inhibit a significant portion of the wave-function fromentering the bottom barrier layer of hetero-structure 104 or a topbarrier layer (e.g., barrier layer 112) formed on quantum-well channelregion 106. In an embodiment, quantum-well channel region 106 has athickness approximately in the range of 150-200 nanometers. In analternative embodiment, quantum-well channel region 106 is composed of asemiconductor material such as, but not limited to, a silicon-germaniumsemiconductor material or a II-VI semiconductor material. In anotheralternative embodiment, quantum-well channel region 106 is a strainedquantum-well region having a thickness approximately in the range of50-100 Angstroms.

Barrier layer 112 may be composed of a material suitable to confine awave-function in a quantum-well formed thereunder. In accordance with anembodiment of the present invention, barrier layer 112 has a latticeconstant suitably matched to the lattice constant of quantum-wellchannel region 106, e.g., the lattice constants are similar enough thatdislocation formation in barrier layer 112 is negligible. In oneembodiment, barrier layer 112 is composed of a layer of material suchas, but not limited to, indium phosphide (InP), gallium nitride (GaN),or indium gallium phosphide (InGaP). In one embodiment, barrier layer112 has a thickness approximately in the range of 1-3 nanometers.

In another aspect of the present invention, a semiconductor deviceincludes a quantum-well channel region with a barrier layer covering theentire quantum-well channel region. FIG. 2 illustrates a cross-sectionalview of a quantum-well-based semiconductor device, in accordance with anembodiment of the present invention.

Referring to FIG. 2, a quantum-well-based semiconductor device 200includes a hetero-structure 204 disposed above a substrate 202 andincluding a quantum-well channel region 206. A barrier layer 212 isdisposed directly on quantum-well channel region 206. A source and drainmaterial region 208 is disposed above barrier layer 212. A trench 210 isdisposed in source and drain material region 208 separating a sourceregion 208A from a drain region 208B. A gate dielectric layer 214 isdisposed in trench 210, between source and drain regions 208A and 208B.A gate electrode 216 is disposed in trench 210, above gate dielectriclayer 214. In accordance with an embodiment of the present invention,hetero-structure 204 may be defined as a stack of one or morecrystalline semiconductor layers, such as the stack depicted in FIG. 2.

In an embodiment, trench 210 exposes the top surface of barrier layer212, and gate dielectric layer 214 is disposed directly on the exposedsurface of barrier layer 212, as depicted in FIG. 2. In anotherembodiment, however, source and drain material region 208 is disposeddirectly on barrier layer 212 (as is depicted), trench 210 is disposedonly partially into source and drain material region 208 leaving aportion of source and drain material region 208 at the bottom of trench210 (not depicted), and gate dielectric layer 214 is disposed directlyon the portion of source and drain material region 208 at the bottom oftrench 210 (not depicted). In an embodiment, quantum-well channel region206 includes a group III-V material, and source and drain materialregion 208 includes a doped group III-V material region. In anembodiment, gate dielectric layer 214 is composed of a high-K materialsuch as, but not limited to, aluminum oxide (Al₂O₃) or hafnium oxide(HfO₂). In an embodiment, gate electrode 216 is a metal gate electrode.In one embodiment, quantum-well channel region 206 includes a groupIII-V material, and source and drain material region 208 includes adoped group III-V material region, gate dielectric layer 214 is composedof a high-K material such as, but not limited to, aluminum oxide (Al₂O₃)or hafnium oxide (HfO₂), and gate electrode 216 is a metal gateelectrode.

Substrate 202 may be composed of a material suitable for semiconductordevice fabrication. In one embodiment, substrate 202 is a bulk substratecomposed of a single crystal of a material which may include, but is notlimited to, silicon, germanium, silicon-germanium or a III-V compoundsemiconductor material. In another embodiment, substrate 202 includes abulk layer with a top epitaxial layer. In a specific embodiment, thebulk layer is composed of a single crystal of a material which mayinclude, but is not limited to, silicon, germanium, silicon-germanium, aIII-V compound semiconductor material or quartz, while the top epitaxiallayer is composed of a single crystal layer which may include, but isnot limited to, silicon, germanium, silicon-germanium or a III-Vcompound semiconductor material. In another embodiment, substrate 202includes a top epitaxial layer on a middle insulator layer which isabove a lower bulk layer. The top epitaxial layer is composed of asingle crystal layer which may include, but is not limited to, silicon(e.g., to form a silicon-on-insulator (SOI) semiconductor substrate),germanium, silicon-germanium or a III-V compound semiconductor material.The insulator layer is composed of a material which may include, but isnot limited to, silicon dioxide, silicon nitride or silicon oxy-nitride.The lower bulk layer is composed of a single crystal which may include,but is not limited to, silicon, germanium, silicon-germanium, a III-Vcompound semiconductor material or quartz. Substrate 202 may furtherinclude dopant impurity atoms.

Hetero-structure 204 may be defined as a stack of one or morecrystalline semiconductor layers, such as a compositional buffer layerwith a bottom barrier layer disposed thereon. The compositional bufferlayer may be composed of a crystalline material suitable to provide aspecific lattice structure onto which a bottom barrier layer may beformed with negligible dislocations. For example, in accordance with anembodiment of the present invention, the compositional buffer layer isused to change, by a gradient of lattice constants, the exposed growthsurface of semiconductor hetero-structure 204 from the lattice structureof substrate 202 to one that is more compatible for epitaxial growth ofhigh quality, low defect layers thereon. In one embodiment, thecompositional buffer layer acts to provide a more suitable latticeconstant for epitaxial growth instead of an incompatible latticeconstant of substrate 202. In an embodiment, substrate 202 is composedof single-crystal silicon and the compositional buffer layer 204 iscomposed of a layer of InAlAs having a thickness of approximately 1micron. In an alternative embodiment, the compositional buffer layer isomitted because the lattice constant of substrate 202 is suitable forthe growth of a bottom barrier layer for a quantum-well semiconductordevice.

The bottom barrier layer may be composed of a material suitable toconfine a wave-function in a quantum-well formed thereon. In accordancewith an embodiment of the present invention, the bottom barrier layerhas a lattice constant suitably matched to the top lattice constant ofthe compositional buffer layer, e.g., the lattice constants are similarenough that dislocation formation in the bottom barrier layer isnegligible. In one embodiment, the bottom barrier layer is composed of alayer of approximately In_(0.65)Al_(0.35)As having a thickness ofapproximately 10 nanometers. In a specific embodiment, the bottombarrier layer composed of the layer of approximatelyIn_(0.65)Al_(0.35)As is used for quantum confinement in an N-typesemiconductor device. In another embodiment, the bottom barrier layer iscomposed of a layer of approximately In_(0.65)Al_(0.35)Sb having athickness of approximately 10 nanometers. In a specific embodiment, thebottom barrier layer composed of the layer of approximatelyIn_(0.65)Al_(0.35)Sb is used for quantum confinement in a P-typesemiconductor device.

Quantum-well channel region 206 may be composed of a material suitableto propagate a wave-function with low resistance. In accordance with anembodiment of the present invention, quantum-well channel region 206 hasa lattice constant suitably matched to the lattice constant of thebottom barrier layer of hetero-structure 204, e.g., the latticeconstants are similar enough that dislocation formation in quantum-wellchannel region 206 is negligible. In an embodiment, quantum-well channelregion 206 is composed of groups III (e.g. boron, aluminum, gallium orindium) and V (e.g. nitrogen, phosphorous, arsenic or antimony)elements. In one embodiment, quantum-well channel region 206 is composedof InAs or InSb. Quantum-well channel region 206 may have a thicknesssuitable to propagate a substantial portion of a wave-function, e.g.suitable to inhibit a significant portion of the wave-function fromentering the bottom barrier layer of hetero-structure 204 or a topbarrier layer (e.g., barrier layer 212) formed on quantum-well channelregion 206. In an embodiment, quantum-well channel region 206 has athickness approximately in the range of 150-200 nanometers. In analternative embodiment, quantum-well channel region 206 is composed of asemiconductor material such as, but not limited to, a silicon-germaniumsemiconductor material or a II-VI semiconductor material. In anotheralternative embodiment, quantum-well channel region 206 is a strainedquantum-well region having a thickness approximately in the range of50-100 Angstroms.

Barrier layer 212 may be composed of a material suitable to confine awave-function in a quantum-well formed thereunder. In accordance with anembodiment of the present invention, barrier layer 212 has a latticeconstant suitably matched to the lattice constant of quantum-wellchannel region 206, e.g., the lattice constants are similar enough thatdislocation formation in barrier layer 212 is negligible. In oneembodiment, barrier layer 212 is composed of a layer of material suchas, but not limited to, indium phosphide (InP), gallium nitride (GaN),or indium gallium phosphide (InGaP). In one embodiment, barrier layer212 has a thickness approximately in the range of 1-3 nanometers.

In another aspect of the present invention, method of forming aquantum-well-based semiconductor device includes a gate-last orreplacement gate approach. FIG. 3 is a Flowchart 400 representingoperations in the fabrication of a quantum-well-based semiconductordevice, in accordance with an embodiment of the present invention. FIGS.4A-4F illustrate cross-sectional views representing operations in thefabrication of a quantum-well-based semiconductor device, in accordancewith an embodiment of the present invention.

Referring to operation 302 of Flowchart 300 and corresponding FIG. 4A, amethod of forming a quantum-well-based semiconductor device includesproviding a hetero-structure 404 disposed above a substrate 402 andincluding a quantum-well channel region 406.

Substrate 402 may be composed of a material suitable for semiconductordevice fabrication. In one embodiment, substrate 402 is a bulk substratecomposed of a single crystal of a material which may include, but is notlimited to, silicon, germanium, silicon-germanium or a III-V compoundsemiconductor material. In another embodiment, substrate 402 includes abulk layer with a top epitaxial layer. In a specific embodiment, thebulk layer is composed of a single crystal of a material which mayinclude, but is not limited to, silicon, germanium, silicon-germanium, aIII-V compound semiconductor material or quartz, while the top epitaxiallayer is composed of a single crystal layer which may include, but isnot limited to, silicon, germanium, silicon-germanium or a III-Vcompound semiconductor material. In another embodiment, substrate 402includes a top epitaxial layer on a middle insulator layer which isabove a lower bulk layer. The top epitaxial layer is composed of asingle crystal layer which may include, but is not limited to, silicon(e.g., to form a silicon-on-insulator (SOI) semiconductor substrate),germanium, silicon-germanium or a III-V compound semiconductor material.The insulator layer is composed of a material which may include, but isnot limited to, silicon dioxide, silicon nitride or silicon oxy-nitride.The lower bulk layer is composed of a single crystal which may include,but is not limited to, silicon, germanium, silicon-germanium, a III-Vcompound semiconductor material or quartz. Substrate 402 may furtherinclude dopant impurity atoms.

Hetero-structure 404 may be defined as a stack of one or morecrystalline semiconductor layers, such as a compositional buffer layerwith a bottom barrier layer disposed thereon. The compositional bufferlayer may be composed of a crystalline material suitable to provide aspecific lattice structure onto which a bottom barrier layer may beformed with negligible dislocations. For example, in accordance with anembodiment of the present invention, the compositional buffer layer isused to change, by a gradient of lattice constants, the exposed growthsurface of semiconductor hetero-structure 404 from the lattice structureof substrate 402 to one that is more compatible for epitaxial growth ofhigh quality, low defect layers thereon. In one embodiment, thecompositional buffer layer acts to provide a more suitable latticeconstant for epitaxial growth instead of an incompatible latticeconstant of substrate 402. In an embodiment, substrate 402 is composedof single-crystal silicon and the compositional buffer layer 404 iscomposed of a layer of InAlAs having a thickness of approximately 1micron. In an alternative embodiment, the compositional buffer layer isomitted because the lattice constant of substrate 402 is suitable forthe growth of a bottom barrier layer for a quantum-well semiconductordevice.

The bottom barrier layer may be composed of a material suitable toconfine a wave-function in a quantum-well formed thereon. In accordancewith an embodiment of the present invention, the bottom barrier layerhas a lattice constant suitably matched to the top lattice constant ofthe compositional buffer layer, e.g., the lattice constants are similarenough that dislocation formation in the bottom barrier layer isnegligible. In one embodiment, the bottom barrier layer is composed of alayer of approximately In_(0.65)Al_(0.35)As having a thickness ofapproximately 10 nanometers. In a specific embodiment, the bottombarrier layer composed of the layer of approximatelyIn_(0.65)Al_(0.35)As is used for quantum confinement in an N-typesemiconductor device. In another embodiment, the bottom barrier layer iscomposed of a layer of approximately In_(0.65)Al_(0.35)Sb having athickness of approximately 10 nanometers. In a specific embodiment, thebottom barrier layer composed of the layer of approximatelyIn_(0.65)Al_(0.35)Sb is used for quantum confinement in a P-typesemiconductor device. In accordance with an embodiment of the presentinvention, the compositional buffer layer and the bottom barrier layerare deposited by a molecular-beam epitaxy technique performed on thesurface of substrate 402.

Quantum-well channel region 406 may be composed of a material suitableto propagate a wave-function with low resistance. In accordance with anembodiment of the present invention, quantum-well channel region 406 hasa lattice constant suitably matched to the lattice constant of thebottom barrier layer of hetero-structure 404, e.g., the latticeconstants are similar enough that dislocation formation in quantum-wellchannel region 406 is negligible. In an embodiment, quantum-well channelregion 406 is composed of groups III (e.g. boron, aluminum, gallium orindium) and V (e.g. nitrogen, phosphorous, arsenic or antimony)elements. In one embodiment, quantum-well channel region 406 is composedof InAs or InSb. Quantum-well channel region 406 may have a thicknesssuitable to propagate a substantial portion of a wave-function, e.g.suitable to inhibit a significant portion of the wave-function fromentering the bottom barrier layer of hetero-structure 404 or a topbarrier layer (e.g., barrier layer 412) formed on quantum-well channelregion 406. In an embodiment, quantum-well channel region 406 has athickness approximately in the range of 150-200 nanometers. In analternative embodiment, quantum-well channel region 406 is composed of asemiconductor material such as, but not limited to, a silicon-germaniumsemiconductor material or a II-VI semiconductor material. In anotheralternative embodiment, quantum-well channel region 406 is a strainedquantum-well region having a thickness approximately in the range of50-100 Angstroms.

Referring to operation 304 of Flowchart 300 and corresponding FIG. 4B, amethod of forming a quantum-well-based semiconductor device includesforming a source and drain material region 408 above quantum-wellchannel region 406. In accordance with an embodiment of the presentinvention, quantum-well channel region 406 includes a group III-Vmaterial, and forming source and drain material region 408 includesforming a doped group III-V material region. In one embodiment, formingquantum-well channel region 406 includes depositing a materialcomposition by molecular-beam epitaxy.

Referring to operation 306 of Flowchart 300 and corresponding FIG. 4C, amethod of forming a quantum-well-based semiconductor device includesforming a trench 410 in source and drain material region 408 to providea source region 408A separated from a drain region 408B. In accordancewith an embodiment of the present invention, trench 410 is formed by adry or wet etch process and the top surface of quantum-well channelregion 406 acts as an etch stop, as depicted in FIG. 4C. In accordancewith an alternative embodiment of the present invention, trench 410 isformed by a dry or wet etch process and the top surface of a barrierlayer acts as an etch stop. In accordance with another alternativeembodiment of the present invention, trench 410 is formed by a dry orwet etch process which is halted prior to completely etching throughsource and drain material region 408.

Referring to FIG. 4D, a method of forming a quantum-well-basedsemiconductor device includes forming a barrier layer 412. In accordancewith an embodiment of the present invention, prior to forming gatedielectric layer 414, barrier layer 412 is formed in trench 410, asdepicted in FIG. 4D. In one embodiment, forming trench 410 includesexposing the top surface of quantum-well channel region 406 (as depictedin FIG. 4C), and forming barrier layer 412 includes forming barrierlayer 412 directly on the exposed surface of quantum-well channel region406 (as depicted in FIG. 4D). In another embodiment, forming source anddrain material region 408 includes forming source and drain materialregion 408 directly on quantum-well channel region 406 (as shown in FIG.4B), forming trench 410 includes etching only partially into source anddrain material region 408 to leave a portion of source and drainmaterial region 408 at the bottom of trench 410 (not shown), and formingbarrier layer 412 includes forming barrier layer 412 directly on theportion of source and drain material region 408 at the bottom of trench410 (not shown). In an embodiment, prior to forming barrier layer 412,source and drain material region 408 is heated to a temperatureapproximately at, or above, 550 degrees Celsius.

In accordance with an alternative embodiment of the present invention,prior to forming source and drain material region 408, barrier layer 412is formed directly on quantum-well channel region 406 (not shown). Inone embodiment, forming trench 410 includes exposing the top surface ofbarrier layer 412, and forming gate dielectric layer 414 includesforming gate dielectric layer 414 directly on the exposed surface ofbarrier layer 414. In another embodiment, forming source and drainmaterial region 408 includes forming source and drain material region408 directly on barrier layer 412, forming trench 410 includes etchingonly partially into source and drain material region 408 to leave aportion of source and drain material region 408 at the bottom of trench410, and forming gate dielectric layer 414 includes forming the gatedielectric layer 414 directly on the portion of source and drainmaterial region 408 at the bottom of trench 410.

Barrier layer 412 may be composed of a material suitable to confine awave-function in a quantum-well formed thereunder. In accordance with anembodiment of the present invention, barrier layer 412 has a latticeconstant suitably matched to the lattice constant of quantum-wellchannel region 406, e.g., the lattice constants are similar enough thatdislocation formation in barrier layer 412 is negligible. In oneembodiment, barrier layer 412 is composed of a layer of material suchas, but not limited to, indium phosphide (InP), gallium nitride (GaN),or indium gallium phosphide (InGaP). In accordance with an embodiment ofthe present invention, forming barrier layer 412 includes forming, byatomic layer deposition, a layer of material such as, but not limitedto, indium phosphide (InP), gallium nitride (GaN), or indium galliumphosphide (InGaP). In one embodiment, barrier layer 412 has a thicknessapproximately in the range of 1-3 nanometers.

Referring to operation 308 of Flowchart 300 and corresponding FIG. 4E, amethod of forming a quantum-well-based semiconductor device includesforming a gate dielectric layer 414 in trench 410, between the sourceand drain regions 408A and 408B. In accordance with an embodiment of thepresent invention, gate dielectric layer 414 is composed of a high-Kmaterial such as, but not limited to, aluminum oxide (Al₂O₃) or hafniumoxide (HfO₂).

Referring to operation 310 of Flowchart 300 and corresponding FIG. 4F, amethod of forming a quantum-well-based semiconductor device includesforming a gate electrode 416 in trench 410, above gate dielectric layer414. In accordance with an embodiment of the present invention, gateelectrode 416 is a metal gate electrode. In one embodiment, gateelectrode 416 is composed of a material such as, but not limited to, ametal nitride, a metal carbide, a metal silicide, hathium, zirconium,titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt ornickel.

Thus, quantum-well-based semiconductor devices and methods of formingquantum-well-based semiconductor devices have been disclosed. Inaccordance with an embodiment of the present invention, a methodincludes providing a hetero-structure disposed above a substrate andincluding a quantum-well channel region. A source and drain materialregion is formed above the quantum-well channel region. A trench isformed in the source and drain material region to provide a sourceregion separated from a drain region. A gate dielectric layer is formedin the trench, between the source and drain regions. A gate electrode isformed in the trench, above the gate dielectric layer. In oneembodiment, the method further includes, prior to forming the gatedielectric layer, forming a barrier layer in the trench. In a specificembodiment, the method further includes prior to forming the barrierlayer, heating the source and drain material region to a temperatureapproximately at, or above, 550 degrees Celsius. In another specificembodiment, forming the barrier layer includes forming, by atomic layerdeposition, a layer of material such as, but not limited to, indiumphosphide (InP), gallium nitride (GaN), or indium gallium phosphide(InGaP). In one embodiment, the method further includes, prior toforming the source and drain material region, forming a barrier layerdirectly on the quantum-well channel region.

What is claimed is:
 1. A method of forming a quantum-well-basedsemiconductor device, the method comprising: providing ahetero-structure disposed above a substrate and comprising aquantum-well channel region; forming a source and drain material regionabove the quantum-well channel region; forming a trench in the sourceand drain material region to provide a source region separated from adrain region; forming a barrier layer in the trench, wherein forming thetrench comprises exposing a top surface of the quantum-well channelregion, and wherein forming the barrier layer comprises forming thebarrier layer directly on the exposed surface of the quantum-wellchannel region; and subsequent to forming the barrier layer, forming agate dielectric layer in the trench, between the source and drainregions; and forming a gate electrode in the trench, above the gatedielectric layer.
 2. The method of claim 1, further comprising: prior toforming the barrier layer, heating the source and drain material regionto a temperature approximately at, or above, 550 degrees Celsius.
 3. Themethod of claim 1, wherein forming the barrier layer comprises forming,by atomic layer deposition, a layer of material selected from the groupconsisting of indium phosphide (InP), gallium nitride (GaN), and indiumgallium phosphide (InGaP).
 4. The method of claim 1, wherein thequantum-well channel region comprises a group III-V material, andwherein forming the source and drain material region comprises forming adoped group III-V material region.
 5. A method of forming aquantum-well-based semiconductor device, the method comprising:providing a hetero-structure disposed above a substrate and comprising aquantum-well channel region; forming a source and drain material regionabove the quantum-well channel region; forming a trench in the sourceand drain material region to provide a source region separated from adrain region; forming a barrier layer in the trench, wherein forming thesource and drain material region comprises forming the source and drainmaterial region directly on the quantum-well channel region, whereinforming the trench comprises etching only partially into the source anddrain material region to leave a portion of the source and drainmaterial region at a bottom of the trench, and wherein forming thebarrier layer comprises forming the barrier layer directly on theportion of the source and drain material region at the bottom of thetrench; and subsequent to forming the barrier layer, forming a gatedielectric layer in the trench, between the source and drain regions;and forming a gate electrode in the trench, above the gate dielectriclayer.
 6. The method of claim 5, further comprising: prior to formingthe barrier layer, heating the source and drain material region to atemperature approximately at, or above, 550 degrees Celsius.
 7. Themethod of claim 5, wherein forming the barrier layer comprises forming,by atomic layer deposition, a layer of material selected from the groupconsisting of indium phosphide (InP), gallium nitride (GaN), and indiumgallium phosphide (InGaP).
 8. The method of claim 5, wherein thequantum-well channel region comprises a group III-V material, andwherein forming the source and drain material region comprises forming adoped group III-V material region.
 9. A method of forming aquantum-well-based semiconductor device, the method comprising:providing a hetero-structure disposed above a substrate and comprising aquantum-well channel region; forming a barrier layer directly on thequantum-well channel region; subsequent to forming the barrier layer,forming a source and drain material region above the quantum-wellchannel region; forming a trench in the source and drain material regionto provide a source region separated from a drain region; forming a gatedielectric layer in the trench, between the source and drain regions,wherein forming the source and drain material region comprises formingthe source and drain material region directly on the barrier layer,wherein forming the trench comprises etching only partially into thesource and drain material region to leave a portion of the source anddrain material region at a bottom of the trench, and wherein forming thegate dielectric layer comprises forming the gate dielectric layerdirectly on the portion of the source and drain material region at thebottom of the trench; and forming a gate electrode in the trench, abovethe gate dielectric layer.
 10. The method of claim 9, wherein thequantum-well channel region comprises a group III-V material, andwherein forming the source and drain material region comprises forming adoped group III-V material region.
 11. The method of claim 9, whereinforming the barrier layer comprises forming, by atomic layer deposition,a layer of material selected from the group consisting of indiumphosphide (InP), gallium nitride (GaN), and indium gallium phosphide(InGaP).